This invention relates to a method of producing MOS transistors with flat source/drain zones, short channel lengths, and a self aligning contacting plane consisting of a metal silicide.
Reducing the structure sizes of integrated MOS circuits requires diminishing the depth of penetration of the source/drain diffusion zones. Consequently, the series resistance increases considerably. This resistance decreases the current amplification of the transistor, so that, from a channel length of 1 to 0.5 microns and on a further miniaturization of the structure offers no advantage.
Possibilities for reducing the unacceptably high series resistance of the source/drain zones are provided by self-aligned silicide plating of these zones with platinum silicide as described in an article by Shibata et al. in IEEE, ED 29 (1982) at pages 531 to 535. After the source/drain implantation, SiO.sub.2 is deposited from the gaseous phase and thereafter etched anisotropically, that is, with steep edges, so that an edge covering occurs at the gate edges (sidewall spacer oxide). Thereafter platinum is vapor deposited and sintered. Thus a silicide layer develops in self-alignment both on the gate electrode and on the source/drain zones.
The disadvantages of this method, other than the complicated process involved, are:
(a) consumption of silicon during the silicide plating, which may lead to short circuits to the substrate in case of shallow diffusion zones,
(b) thermal stability is ensured for temperature lower than 700.degree. C. only, and
(c) a complicated metallization system with diffusion barrier is required and because of the multiple layer construction etching problems may occur.
Another possibility for reducing the source/drain series resistances is, as has been proposed in German patent application No. P 32 43 125.2, to produce self aligned poly-silicon contacts on the source/drain zones, the source/drain zones being formed by out-diffusion from the doped polysilicon layer which later serves as contact terminal.